`timescale 1ns / 1ps
`include "defines.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/11 17:50:27
// Design Name: 
// Module Name: Latch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

// 锁存器,用于实现CPU的流水线结构,默认总线宽度为32
module Latch#(parameter DW = 32)
    (
    input [0:0] clk,
    input [0:0] rst,

    input [0:0] Clear_Flag,  //流水线暂停标志
    input [DW-1:0] Default_Value,  //默认值


    input [DW-1:0] Write_Input,  //写入
    output [DW-1:0] Read_Output //输出
    );


    reg[DW-1:0] Reg_WR;


    always @ (posedge clk) begin

        if ((rst == `Rst_Enabled) | Clear_Flag == `Clear_Flag_Enabled) begin
            Reg_WR <= Default_Value; 
        end else begin
            Reg_WR <= Write_Input;
        end
    end

    assign Read_Output = Reg_WR;

endmodule
